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DV Engineer


This is a Full-time position in Menlo Park, CA posted June 8, 2021.

Title Design Verification Engineer (ASIC, RTL) System Verilog RTL design i. 8-10 yrs min of hands on FPGA digital design ii. Experience with Architecture to uArchitecture handoff i.e. can work with an architect to distill architecture into uArchitecture iii. Experience with owning uArchitecture through RTL implementation iv. Understands FPGA logic, RAM, and how to design small designs that can efficiently close timing Top level chip stitching and integration of i. Custom built design modules (delivered as IP from resources such as a. above ii. Xilinx IP blocks iii. Xilinx clocks and clock management structures iv. IOs, including IO bank management Xilinx FPGAs i. Preferably Xilinx Versal FPGAs ii. Experience with embedded system buses such as CAN, I2C, RGMII Ethernet, I3C, SPI iii. Hands on experience with off the shelf Xilinx development systems, preferably Versal development boards Embedded Control Systems domain experience i. CAN, I2C, RGMII Ethernet, I3C, SPI Interlaken Experience integrating DSP functions, specifically a MODEM would be a bit plus Experience with ARM processors on FPGA i. Petalinux experience ii. RTOS experience